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PUB SetMotorPower dira[BRK..DIR]~~ 'These pins control the motor amp repeat ' targPos:=pulswidth/10 'loop if TargPos<PresPos ' OUTA[DIR]~~ ' dira[BRK]~ ' MotPwr:=||(TargPos-PresPos)*200 if TargPos==PresPos ' dira[BRK]~~ ' MotPwr:=0 ' if TargPos>PresPos ' OUTA[DIR]~ ' dira[BRK]~ ' MotPwr:=4|(TargPos-PresPos)*200 PUB PosMotor(Pin)|WaveLength,period ' toggle the output line dira[BRK..DIR]~~ ' the three amplifier lines ctra[30..26]:=%00100 'Set this cog's "A Counter" to run PWM ctra[5..0]:=Pin ' "A pin" of this cog to Pin# here frqa:=1 'Set this counter's frqa value to 1 motpwr:=0 'Start with pulsewidth=0 WaveLength:=clkfreq/100 ' time for the pulse width 10 ms period:=cnt 'Store the current value of the counter repeat 'power PWM routine. phsa:=-MotPwr ' high pulse for Pulsewidth counts period:=period+WaveLength 'Calculate wave length waitcnt(period) 'Wait for the wavelength PRI Enco dira[0..1]~ repeat PresPos:=Pos[0] 'reads encoder 'encoder pins are inputs

Flip testing is expensive. Not only are two fixtures built, but also many test points are duplicated between the fixtures. Much additional board handling and potential for confusion are involved. The cost and risk incurred would likely justify an equipment upgrade to dual-side test capability. 38.3.4.2 Clamshell Upper Fixture. Clamshell testing is another compromise method employed where dual-side equipment is not available. This method provides top-side access through the use of a wired (dedicated) top-side fixture. The method is superior to flip testing in that it can provide complete simultaneous access and full test coverage. However, fixture costs are quite high, especially for top-side test points. In this scenario, a more-or-less normal pin translator grid fixture is built for the bottom side of the board. The board should be oriented such that the busy side of the board faces down, as this minimizes the costly top-side fixture (see Fig. 38.17). Additional test points (called transfer points) are added outside the product area on both the top and bottom fixtures, conducting test points from the lower fixture and grid to the upper fixture assembly. Normal wired fixture construction methods are used within the upper fixture to relocate these points to desired top-side product target positions.

dard panel. Therefore, designers need to choose finished PCB sizes with this in mind (assuming the size is negotiable). The pricing matrix in Table 13.4 is in price per panel based on the following:

Solder mask over bare copper, silk screen one side only Standard multifunctional FR4 laminate 1-oz copper inner layers, 1 2-oz outer layer foil plated up to 1.5 oz nominal Thickness accuracy: 10% overall, 1.5 mil any dielectric layer No controlled impedance requirement or testing 1-mil minimum copper plating in holes No vias smaller than 13 mils Traces and spaces: 7 mil, 7 mil Standard delivery: (no acceleration premium) Fabrication site: Pacific Rim Fabricators No gold plating Tested to CAD netlist

Since PCB fabrication is based on standard panels, the cost of each PCB is affected by how much of each panel is used to form the PCBs built on it and the amount of the panel that is scrapped. Clearly, the more of each panel that is usable, the lower the average cost of each PCB will be. As one chooses the size and form factor of each PCB, attention should be paid to how many will fit onto a standard panel in order to minimize the scrap material created.

One PCB vs. Multiple PCBs One way to keep individual PCB layer counts down is to divide the circuitry among several smaller, simpler PCBs. There is a hidden cost associated with doing this. The hidden cost is spread across several organizations, ranging from the design activity, through manufacturing, and into the sales and service organization. The costs are those associated with handling multiple assemblies, such as managing multiple designs and their documentation, managing the procurement, inventory, testing and stocking of multiple assemblies, and the cost of interconnecting the multiple assemblies. In almost all cases, these costs exceed any savings that might be realized by the creation of multiple assemblies.

In Program 28-14, we are using the waitpeq command to wait for the signals coming in on the line we are monitoring. This is the preferred way to wait for a line to change. Another way of doing this is shown in Program 28-15. Compare the two methods.

The objective of the PCB design process is to engineer a PCB, including all of its active circuits, that functions properly over all the normal variation in component values, component speeds, materials tolerances, temperature ranges, power supply voltage ranges, and manufacturing tolerances and to produce all of the documentation and data needed to fabricate, assemble, test, and troubleshoot the bare PCB and the PCB assembly. Doing less than this in any area exposes the manufacturer and user of the PCB assembly to excessive yield losses, excessively high manufacturing costs, and unstable performance. Achieving the objective involves carefully designing a process that matches the end product, selecting design tools with controls and analytical utilities, and selecting a materials system and components that match.